19M111RIP - Development and application of computer hardware accelerators

Course specification
Course title		Development and application of computer hardware accelerators
Acronym		19M111RIP
Study programme
Module
Type of study
Lecturer (for classes)		asst. professor PhD Živojin Šuštran professor PhD Veljko Milutinović
Lecturer/Associate (for practice)		asst. professor PhD Živojin Šuštran professor PhD Veljko Milutinović
Lecturer/Associate (for OTC)		asst. professor PhD Živojin Šuštran
ESPB		6.0	Status	elective
Condition		None.
The goal		The aim of the course is for students to become familiar with the modern way of developing computer accelerators (CA) and acquire theoretical and practical knowledge for the analysis, development, implementation and testing of CA. Teach students to recognize when CA can achieve speedups compared to general-purpose processors, with less power consumption, and how to use a greater flexibility of CA.
The outcome		Students are expected to develop the ability to understand and independently develop modern systems based on computer accelerators (CA. Also, students are expected to develop the ability to program CA at higher levels of abstraction, as well as to compare different paradigms by parameters such as speed and power consumption.
Contents
URL to the subject page		https://rti.etf.bg.edu.rs/rti/ms1rip/
Contents of lectures		The course analyzes the development of supercomputers, defines the DataFlow (DF) paradigm for the development of computer accelerators, presents its advantages and introduces students to the DF programming model. The course covers all phases of system development based on the DF paradigm: algorithm design, program compilation, system software, methods for improving algorithms.
Contents of exercises		Practical teaching includes analysis of program development tools on DataFlow computing accelerators (CA). During practical exercises, students are introduced to a number of examples of application of CA in the following areas: mathematical algorithms, image processing, machine learning, tensor calculus. Individual homework: development and testing of a CA for computationally demanding problems.
Literature
Stojanovic, S., Bojic, D., Bojovic, M., "An Overview of Selected Heterogeneous and Reconfigurable Architectures," Advances in Computers, 2015 (Original title) Korolija, N., Popovic, J., Cvetanovic, M., Bojovic, M., "Dataflow-Based Parallelization of Control-Flow Algorithms," Advances in Computers, 2017 (Original title) Milutinovic, V., et al, "DataFlow SuperComputing Essentials," Springer, 2017 (Original title) Flynn, M., Mencer, O., Milutinovic, V., et al, “Moving from PetaFlops to PetaData,” Communications of the ACM, 2013 (Original title) Milutinovic, V., "Mapping of neural networks on the honeycomb architecture," Proceedings of the IEEE, 1989 (Original title)
Number of hours per week during the semester/trimester/year
Lectures	Exercises	OTC	Study and Research	Other classes
2	2	1
Methods of teaching		Lectures are held with electronic presentations. The lectures introduce concepts and explain the definition of computer accelerators (CA). During the auditory exercises, practical examples of the development of DataFlow CA are demonstrated. The course includes several homework assignments in the areas of mathematical algorithms, image processing, machine learning, and tensor calculus.
Knowledge score (maximum points 100)
Pre obligations		Points	Final exam	Points
Activites during lectures		0	Test paper	0
Practical lessons		0	Oral examination	30
Projects		70
Colloquia		0
Seminars		0