13E112AR - Computer Architecture

Course specification
Course title		Computer Architecture
Acronym		13E112AR
Study programme		Electrical Engineering and Computing
Module		Computer Engineering and Informatics
Type of study		bachelor academic studies
Lecturer (for classes)		professor PhD Zaharije Radivojević
Lecturer/Associate (for practice)		asst. professor PhD Uroš Radenković Miloš Milošević, electrical and computer engineer asst. MA Danko Miladinović, electrical and computer engineer
Lecturer/Associate (for OTC)		asst. professor PhD Uroš Radenković asst. MA Danko Miladinović, electrical and computer engineer Miloš Milošević, electrical and computer engineer
ESPB		6.0	Status	mandatory
Condition		Fundamentals of Computer Engineering 2
The goal		Introduce concepts of CISC and RISC architectures, interrupts and structure of buses and input/output systems.
The outcome		By the end of this course, students will be able to: understand structure and functioning of a CISC and RISC types of processors, buses, and input/output systems; and to use literature with the aim to deepen their knowledge in these fields.
Contents
URL to the subject page		https://rti.etf.bg.edu.rs/rti/ef2ar/index.html
URL to lectures		https://teams.microsoft.com/l/team/19%3aBePrjwJxbmOSaZB21ZRBMRDRb9iBYAhX4ZpVZzH9hW41%40thread.tacv2/conversations?groupId=78f15fc2-5c36-4c37-bb89-00a773010925&tenantId=1774ef2e-9c62-478a-8d3a-fd2a495547ba
Contents of lectures		Architecture. CISC and RISC. Programming model. Data types. Instruction formats. Addressing modes. Instruction set. Interrupt. Bus. Arbitration. Buses with atomic and split transaction cycles. Multiple buses. Input/output. Devices and device controllers. Programming. Interrupts handling - polling and vectorising.
Contents of exercises		Architecture. CISC and RISC. Programming model. Data types. Instruction formats. Addressing modes. Instruction set. Interrupt. Bus. Arbitration. Buses with atomic and split transaction cycles. Multiple buses. Input/output. Devices and device controllers. Programming. Interrupts handling - polling and vectorising.
Literature
J. Đorđević, Computer Architecture and Organization, http://rti.etf.bg.edu.rs/ J. Đorđević, Computer Architecture and Organization, Collection of solved problems, http://rti.etf.bg.edu.rs/ William Stallings - Computer Organization and Architecture, Global Edition 11th Edition, 2021 A. Tanenbaum, T. Austin, Structured Computer Organization, Prentice Hall, 2013 J. Đorđević, Computer Architecture and Organization, Materials for laboratory exercises, http://rti.etf.bg.edu.rs/
Number of hours per week during the semester/trimester/year
Lectures	Exercises	OTC	Study and Research	Other classes
2	2	1
Methods of teaching		Lectures, exercises and laboratory exercises.
Knowledge score (maximum points 100)
Pre obligations		Points	Final exam	Points
Activites during lectures		0	Test paper	30
Practical lessons		20	Oral examination	0
Projects
Colloquia		50
Seminars		0