Verification beyond the chip

Lecture and presentation of book “ASIC AND FPGA VERIFICATION A GUIDE TO COMPONENT MODELING”

Content:

– Component modeling in VHDL/VITAL
– Using VITAL to Simulate Your RTL
– Board-level verification
– Guide of best practices for developing VHDL/VITAL models
– One typical case study of boardlevel verification

Biography:

Richard Munden has been using and managing CAE systems since 1987. He
has been concerned with simulation and modeling issues for as long.

He cofounded the Free Model Foundry (http://eda.org/fmf/) in 1995 and is its
president and CEO. He has a day job as CAE/PCB manager at Siemens
Ultrasound (previously Acuson Corp) in Mountain View, CA. Prior to joining
Acuson, he was a CAE manager at TRW in Redondo Beach, CA. He is a well
known contributor to several EDA users groups and industry conferences.

His primary focus over the years has been verification of boardlevel designs.