An Energy Efficient Parallel Architecture Using Near Threshold Operation

Abstract

Subtreshold circuit design, while energy efficient, has the drawback of performance degradation. To retain the excellent energy efficiency while reducing performance loss, we propose to investige near subtreshold techniques on chip multiprocessors (CMP). We show that logic and memory cells have different optimal supply and treshold voltages; therefore, we propose to allow the cores and memory to operate in different voltage regions. With the memory operating at a different voltage, we then explore the design space in which several slower core clustered together share a faster L1 cache. We show that an architecture such as this is optimal for energy efficiency. In addition we explore the design tradeoffs that occur if we have separate instruction and data caches. We show that some applications prefer the data cache to be clustered, while the instruction cache is kept private to the core allowing further energy savings of a 77% reduction over a single core machine.